This invention relates to the fabrication of multilayer ceramic substrates and, more particularly, relates to the forming of an electrically conductive surface pad using thick film techniques that has improved mechanical and electrical reliability.
Multilayer ceramic substrates are typically used for interconnection between integrated circuit devices used in information processing systems such as computers, control systems and circuit boards and are traditionally made using two processes. The oldest process is a layer build up process that starts with a fired ceramic layer onto which alternating patterned layers of dielectric and metal conductive layers are sequentially deposited by a screening operation to form a multilayer structure. These can be sintered after each deposition or sintered after all the layers are deposited. Sintering at sufficiently high temperatures consolidates the metal, ceramic and usually glass particles into a dense, impervious monolith that provides mechanical support of the electrically continuous circuit traces formed within the ceramic dielectric.
Another method to make multilayer ceramic substrates involves forming the dielectric into a tape by using a casting process, punching the tape to form holes or "vias" into which a conductive metal paste is deposited along with metal traces that act as wiring. A number of these punched and metallized tapes are aligned, stacked and pressed into a laminate that is subsequently sintered. Such a methodology is a cofired process in which the ceramic and metal powders are consolidated in essentially a single but often complex heating process.
A key element of the sintering process involves the formation of conductive surface features onto which metal plating such as nickel and gold may be deposited, sometimes as preparation for subsequent solder attach processes. These surface features provide connections to the electrical conductors within the ceramic and their mechanical and electrical performance are very important to the reliability of the multilayer ceramic substrate and the entire information processing system.
Traditional ceramic substrates are formed of aluminum oxide (i.e., alumina) which is typically bonded with a fused glass powder after sintering. Sintering of such aluminum oxide ceramic substrates is usually a high temperature process requiring temperatures in excess of 1500.degree. C. Molybdenum and tungsten metal powders are used as the electrical conductor since these provide high electrical conductivity while tolerating this high sintering temperature without melting. These metals also have good thermal expansion match to alumina over the range of temperatures that occur from sintering to sub-ambient testing, typically from 1600.degree. C. to -150.degree. C. respectively. The coefficient of thermal expansion (CTE) of alumina, molybdenum and tungsten are similar at approximately 7, 5 and 4 ppm respectively.
Surface features made using these metals are typically well bonded to the ceramic in a cofiring process by using a glass powder incorporated into the thick film paste used to form the patterned surface feature. The surface features are well adhered and since there is a close CTE match between the surface features and the ceramic, and alumina ceramics are very strong, there is little stress placed on the underlying ceramic during thermal cycling.
The strength of the bond between the surface metal features and the ceramic is important when the surface features, typically present as an array, are electrically connected to a printed circuit board by a solder technique such as ceramic ball grid array (CBGA) and ceramic column grid array (CCGA). In the CBGA attach technique, a solder ball is used as a standoff between the substrate and a printed circuit board. The solder ball has a higher melting temperature than the solder used to attach the ball to the ceramic substrate and the board. Likewise a column of solder wire can be used to effect the connection between the ceramic substrate and the board in the CCGA attach technique.
The reliability of the electrical connection between the ceramic substrate and the board is affected by a number of parameters which include the CTE difference between the ceramic substrate and the board, the stiffness of both, the size of the solder array and the height of the solder join. During thermal cycling, the board expands and contracts much more than the ceramic substrate. This movement causes a large strain in the solder connections between the board and ceramic substrate, the greatest strain occurring at the outermost connections and the least at the center of the solder array. Repetitive thermal cycling eventually fatigues the solder connections to failure and this creates an open in the electrical pathway between the ceramic substrate and board.
Typically, the longer the solder column, the greater the resistance to solder fatigue. CCGAs will withstand many more cycles to failure than CBGAs with all other parameters being equal, however CCGAs are less desirable than CBGAs since CCGAs can be easily damaged in handling and their increased solder length increase inductance which can impair electrical performance.
Information processing systems are increasingly moving towards higher speeds, more power and higher reliability. As part of this migration, the use of higher performance ceramic dielectrics in component packaging for semiconductor devices is becoming wide spread. In particular, the use of ceramic substrates that have increasingly high levels of silica which, when properly combined with other ceramic oxides, results in a lower dielectric constant material to reduce the propagation delay in electronic circuitry is desired. Unlike traditional high alumina ceramics, these ceramic substrates have lower strength and thus are more likely to fracture under loads imposed by solder joining.
Typical of these high performance ceramics are low temperature cofired ceramic systems that use silver or copper as conductors. These high performance ceramics include alumina bonded with low softening point glasses and glass ceramic systems. Unlike the high temperature cofired systems, the CTE differences between these ceramics and the metals are often high. For instance, most of these ceramics have a CTE below 6 ppm while the CTE of silver and copper are 20 and 17 ppm, respectively. Attempts to cofire high metal content surface features on the surface of these low CTE ceramics often results in weak interfaces between the ceramic and surface feature which can become separated during thermal cycling while in processing or use.
It follows then that during cofiring, these metals can be bonded to the ceramic to form high strength joints only by incorporating a large volume of lower CTE compensating filler material, often the same ceramic or glass used to produce the dielectric. This nonconductive filler material in the surface feature can have a severe impact on the electrical conductivity of the feature and cause great difficulty in creating an easily plateable surface feature for a land grid array (LGA) or solder attachment by CBGA or CCGA since the nonconductive portion of the pad will not typically plate with conventional plating baths.
Surface features made with high metal contents often subject the underlying ceramic to severe stresses during thermal cycling due to the large CTE mismatch. Since the high performance ceramic is not as strong as high temperature fired alumina, there is a great tendency to crack the ceramic and eventually cause the electrical connection under the surface feature to fail.
The lack of adhesion between high metal surface features and the underlying ceramic material has been recognized by others. For example, Yokoyama et al. U.S. Pat. No. 5,549,778 and Herron et al. IBM Technical Disclosure Bulletin, 27, No. 8, page 4765 (January 1985), the disclosures of which are incorporated by reference herein, have proposed "dummy" vias to anchor the surface feature to the underlying ceramic. These dummy vias are nonfunctioning and merely serve to mechanically assist in the anchoring of the surface feature.
It would be desirable to have an improved way to anchor the surface feature while providing enhanced electrical and mechanical reliability.
This and other features of the invention will become more apparent after referring to the following description considered in conjunction with the accompanying drawings.